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Fault Tolerance in Safety Critical Applications

The ability to control system failure modes through fault-tolerant design requires an implementation methodology that ensures fault propagation can be controlled. Xilinx Isolation Design Flow (IDF) provides fault containment at the FPGA module level, enabling single-chip fault tolerance by various techniques including:

  • Modular redundancy
  • Watchdog alarms
  • Segregation by safety level
  • Isolation of test logic for safe removal

IDF, pioneered for government cryptographic systems, is also appropriate for avionics, safety-related electronics, industrial robotics, critical infrastructure, financial systems, and other high-assurance, high-availability, and high-reliability systems. The IDF is part of a spectrum of reliability technologies that when appropriately combined provide unmatched reliability, performance, and cost effectiveness.

In addition to it's long heritage serving government grade cryptographic systems, The IDF is an integral part of the Xilinx IEC61508 certified tool chain.  Additionally, it can aid in meeting the requirements of the ISO26262 specification (Automotive Functional Safety).

 

 

 

Device and Software Support

Device Supported Software
Virtex-4 Existing Programs Only
Virtex-5 ISE® 11.4 - ISE latest
Spartan®-6 ISE 13.1 - ISE latest
Kintex®-7​, Zynq®-7000 ISE 14.4 - ISE latest

IDF Methodology

The IDF is a methodology based on existing implementation tool flows (ISE design tools in this case).  Additional time spent floor-planning the design is done using existing constraint tools (PlanAhead™ design tool).  Verification of work products (pinout and routed design) are done with a separate and independent tool called the Isolation Verification Tool (IVT).

idf-design-methodology

block-routed-design-view